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IEEE-754 ARITHMETICDSP ACCELERATIONINTERFACE IPSYNTHESIZABLE RTLFOUNDRY-AGNOSTICLICENSABLE CORESCUSTOM CONFIGURATION
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IP Portfolio

Product portfolio: 11 cores, licensable today.

Arithmetic, DSP and interface IP delivered as soft IP — synthesizable, technology-independent RTL, portable across process nodes and foundries.

11Shipped today
4In active development
15+Total portfolio
RTLTechnology-independent delivery
Browse portfolio

Built for integration,
verification and reuse.

Arithmetic

FP Multiplier

Single-precision floating-point multiplication in synthesizable RTL.

Arithmetic

FP Multiplier-Accumulator

Combined multiply-accumulate operation in one reusable block.

Arithmetic

FP Divider

Floating-point division with IEEE-754 exception handling.

Arithmetic

FP Reciprocal

Optimised reciprocal core with lower latency than a full divider.

Arithmetic

FP Square Root

Standalone floating-point square-root core for graphics and DSP.

Arithmetic

FP Inverse Square Root

Efficient inverse square-root operation without chained blocks.

DSP

FP Complex Multiplier

Complex-number floating-point multiplication for DSP pipelines.

DSP

Complex Matrix Multiplier (N×N)

Configurable matrix multiplication engine and lead differentiator.

Interface

UART

Asynchronous serial interface with standard framing.

Interface

SPI

High-speed synchronous serial master/slave interface.

Interface

I²C

Two-wire multi-device interface with low pin count.

Development

Fixed-Point Complex Multiplier

Fixed-point counterpart for resource-efficient DSP implementations.

Development

NTT / INTT Butterfly Engine

Core building block for lattice cryptography and zk-SNARK systems.

Development

Pippenger MSM Accumulator

Hardware acceleration primitive for zk-SNARK proof generation.

Development

zk-SNARK Primitives

Applied cryptography IP emerging from Zepto Logic research.

Every delivery includes

More than RTL.

RTL

Synthesizable source

Technology-independent RTL designed for portability across target process nodes and foundries.

DV

Verification collateral

Testbenches and supporting material to accelerate integration and qualification.

ENG

Direct engineering support

Access to the engineers who architected, implemented and verified the core.

Engagement models

Five ways to build with us.

01

IP Licensing

  • Per-core or portfolio
  • RTL and verification collateral
  • Direct engineer access
02

Custom Design

  • RTL through physical implementation
  • Verification-first execution
  • Fully owned delivery
03

Staff Augmentation

  • Engineers embedded in your team
  • Flexible programme scaling
04

Turnkey

  • Specification to tape-out-ready
  • Single point of accountability
05

Offshore Development Centre

  • Dedicated Coimbatore engineering centre
  • Ring-fenced for your programme
Connected capability

One centre. Every discipline.

Integrated teams and reusable engineering systems move each programme from definition to validated deliverables without hand-off gaps.

Total IPZepto Logic
01Arithmetic
02DSP
03Interfaces
04Security
05Control
06Custom