RTL to tape-out, start to finish.
Six core stages, verification-first delivery, and one engineering partner accountable from specification through product qualification.
RTL & Digital Design
SystemVerilog/Verilog, lint, CDC and low-power sign-off.
Verification
UVM/VMM, formal, low-power verification and emulation.
FPGA Prototyping
Xilinx and Altera platforms ahead of tape-out.
Physical Design
Synthesis, STA, LEC, floorplan, CTS and routing.
Design for Test
LBIST, MBIST, scan, ATPG and ATE enablement.
Package & Product
Package engineering, product-level testing and validation.
Analog & Mixed-Signal
Power-efficient mixed-signal design capability across advanced and mature process nodes.
Embedded Software
Firmware, drivers, board support, system integration and post-silicon validation.
Mini OSAT, Sulur.
Land allotted under the Tamil Nadu Semiconductor Policy 2022 to build a broader assembly, test, packaging and product engineering capability.
ATMP
- Wafer sort and back-grinding
- Wire bonding, flip-chip and SiP
OSAT
- MCM integration and ATE development
- SI/PI and thermal modelling
PCB Engineering
- 32+ layer, high-speed and RF
- KiCad, Altium and LTSpice
Embedded Systems
- MCU/MPU, RTOS and Linux
- BLE, Wi-Fi, LoRa, GPS and BMS
Designed for PPA.
Delivered for confidence.
Verification-first
Verification begins with the architecture, not as a final gate before delivery.
Integrated delivery
RTL through GDSII under a single accountable engineering engagement.
Reusable IP
Proven arithmetic and interface cores ready to accelerate custom silicon.
Direct access
The engineers who built the core answer the technical questions.
One centre. Every discipline.
Integrated teams and reusable engineering systems move each programme from definition to validated deliverables without hand-off gaps.
Complete Silicon DeliveryZepto Logic